This invention relates generally to complementary metal-oxide-semiconductor (CMOS) output buffer circuits. More particularly, it relates to an output current control circuit for use with CMOS output buffers so as to limit the maximum short circuit current thereof, thereby reducing significantly ground bounce noise.
As is well known, digital logic circuits are widely used in the areas of electronics and computer-type equipment. One such use of digital logic circuits is to provide an interface function between one logic type (i.e., CMOS) of one integrated circuit device and another logic type (i.e., TTL) of another integrated circuit device. An output buffer is an important component for performing this interface function. The output buffer generates, when enabled, an output signal which is a function of a data signal received from other logic circuitry of the integrated circuit.
CMOS output buffer circuit typically use a P-channel pull-up field-effect transistor (FET) and an N-channel pull-down field-effect transistor connected in series between first and second power supply terminals. The first power supply terminal may be supplied with a positive potential which is connected to an internal power supply potential node. The second power supply terminal may be supplied with a ground potential, which is connected to an internal ground potential node. The connection point of the pull-up and pull-down field-effect transistors is further joined to an output terminal.
Dependent upon the logic state of the data input signal and an enable signal, either the pull-up or pull-down field-effect transistor is quickly turned ON and the other one of them is turned OFF. Such rapid switching ON and OFF the pull-up and pull-down field-effect transistors causes sudden surges of current creating what is commonly known as current spikes. These current spikes will flow through the impedance and inductive components of power supply lines so as to cause inductive noise at the internal power supply potential and the internal ground potential nodes of the output buffer. In particular, when the pull-down transistor is quickly turned ON a large instantaneous current cooperates with the line inductance to pull up the internal ground potential which is defined as "ground bounce noise."
There have been attempts made in the prior art at solving this problem of ground bounce noise by driving the pull-down transistor in the output buffer with two different drive sources. One of the drive sources is made to be smaller than the other one and is used to drive ON initially the pull-down transistor. Since this smaller drive source has a smaller current capability, it will tend to slowly turn on the pull-down transistor. Thus, this prior art solution has the disadvantage in that it requires the sacrificing of speed and an increased propagation delay. Then, the larger drive source is used to maintain the pull-down transistor ON so as to provide the needed high current capability. Further, this prior art solution has also the disadvantage of requiring the drive sources to be a function of the load and must be designed for a particular load current.
It would therefore be desirable to provide an output current control circuit for use with CMOS output buffers which reduce significantly ground bounce noise but yet has a high speed of operation and perform independently of the load current. The output current control circuit of the present invention includes a variable resistance device interconnected between a drive source and the gate electrode of the pull-down transistor. The reduction in the ground bounce noise is achieved by increasing the resistance in the variable resistance device in response to a reference voltage generated at the internal ground potential node due to the ground bounce noise. As a result, the maximum short circuit output current in the pull-down transistor is maintained within a certain limit so as to minimize degradation of the propagation delay.